Realizing a quantum computer (QC) with hundreds of qubits in reasonable size is only possible if all related parts are brought close to qubits that are currently operating at cryogenic temperatures (CT). This compels the qubit control and readout part to also function at CT while being placed in the vicinity of qubits. Several technical challenges exist in designing and evaluating an energy-efficient readout and control circuitry, specifically in the digital processing part, to achieve a QC with 100s of qubits working at CT near qubits.
The control and readout subsystems of quantum computers require high-performance digital architectures that consume minimal power to ensure scalability and practical usability. Q-CryCoRe project aims to propose and model low-power digital control and readout section for quantum computers, leveraging principles from cryo-CMOS technology, voltage scaling, and advanced low-power circuit techniques. By adopting state-of-the-art methodologies, this project seeks to deliver an adaptable, efficient, and power-optimized design. Our solution aims to bridge the gap in scalable quantum control using Cryogenic CMOS circuits and systems. This project will not only help accelerate the existing work at UofG. Still, it will also pave the way to have dedicated digital system of quantum computers working on cryogenic temperature.
The objectives of the project are:
• Design a low-power digital architecture for the control and readout subsystem of a quantum computer.
• Develop accurate cryogenic transistor models for digital circuit design.
• Develop and integrate cryo-CMOS technology to minimize power consumption.
The methodology to be followed is presented below:
1. Literature Review:
• Conduct an in-depth study of existing architectures for qubit control/readout and cryo-CMOS technology.
• Examine the current state and challenges in quantum computing, focusing on control and readout mechanisms.
• Review low-power digital design strategies, including dynamic power reduction and static power reduction in digital circuits.
2. Design:
• Develop the architecture for low-power digital circuits tailored for quantum control.
• Create a detailed design for control logic circuits using multi-threshold CMOS and voltage scaling to minimize leakage and dynamic power.
3. Modelling:
• Model the designed circuits using HDL to capture the intended architecture and behaviour.
• Develop cryogenic models by modifying existing SPICE models for accurate simulation at low temperatures.
• Characterize the electrical properties of N- and P-MOS transistors in various CMOS process nodes at cryogenic temperatures to understand mobility changes, leakage currents, and substrate effects.
4. Performance Evaluation:
• Use EDA tools such as provided by Cadence to assess the functionality, area, throughput, and power consumption of the designed circuits.